Method and system for scaling 3d video

ABSTRACT

A method and system are provided in which an integrated circuit (IC) comprises multiple devices that may be selectively interconnected to route and process 3D video data. The IC may be operable to determine whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from memory, and selectively interconnect one or more of the devices based on the determination. The selective interconnection may be based on input and output formats of the 3D video data, and on a scaling factor. The input format may be a left-and-right (L/R) format or an over-and-under (O/U) format. Similarly, the output format may be a L/R format or an O/U format. The selective interconnection may be based on input and output pixel rates of the 3D video data. Moreover, the selective interconnection may be determined on a picture-by-picture basis.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to, claims priority to, and claims thebenefit of:

U.S. Provisional Patent Application Ser. No. 61/267,729 (Attorney DocketNo. 20428US01) filed on Dec. 8, 2009;U.S. Provisional Patent Application Ser. No. 61/296,851 (Attorney DocketNo. 22866US01) filed on Jan. 20, 2010; andU.S. Provisional Patent Application Ser. No. 61/330,456 (Attorney DocketNo. 23028US01) filed on May 3, 2010.

This application also makes reference to:

U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No.20428U502) filed on Dec. 8, 2010;U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No.23438U502) filed on Dec. 8, 2010;U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No.23439U502) filed on Dec. 8, 2010; andU.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No.23440U502) filed on Dec. 8, 2010.

Each of the above referenced applications is hereby incorporated hereinby reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to processing ofthree-dimensional (3D) video. More specifically, certain embodiments ofthe invention relate to a method and system for scaling 3D video.

BACKGROUND OF THE INVENTION

The availability and access to 3D video content continues to grow. Suchgrowth has brought about challenges regarding the handling of 3D videocontent from different types of sources and/or the reproduction of 3Dvideo content on different types of displays.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for scaling 3D video, as set forth morecompletely in the claims.

Various advantages, aspects and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram that illustrates a system-on-chip that isoperable to handle 3D video data scaling, in accordance with anembodiment of the invention.

FIGS. 2A-2E illustrate various input and output packing schemes for 3Dvideo data, in accordance with embodiments of the invention.

FIGS. 3A-3C are block diagrams that illustrate a processing network thatis operable to scale 3D video data, in accordance with embodiments ofthe invention.

FIGS. 4A and 4B illustrate format-related variables for left-and-right(L/R) format and over-and-under (O/U) format, respectively, inaccordance with embodiments of the invention.

FIGS. 5A and 5B illustrate configurations of the processing network whenscaling 3D video data from an L/R input format to an L/R output format,in accordance with embodiments of the invention.

FIGS. 6A and 6B illustrate configurations of the processing network whenscaling 3D video data from an L/R input format to an O/U output format,in accordance with embodiments of the invention.

FIGS. 7A and 7B illustrate configurations of the processing network whenscaling 3D video data from an O/U input format to an L/R output format,in accordance with embodiments of the invention.

FIGS. 8A and 8B illustrate configurations of the processing network whenscaling 3D video data from an O/U input format to an O/U output format,in accordance with embodiments of the invention.

FIG. 9 is a diagram that illustrates an example of scaling on thecapture side when the 3D video has a 1080p O/U input format and a 720pL/R output format, in accordance with an embodiment of the invention.

FIGS. 10A and 10B are block diagrams that illustrate the order in whichadditional video processing operations may be performed in a processingnetwork configured for scaling 3D video data, in accordance withembodiments of the invention.

FIG. 11 is a flow chart that illustrates steps for scaling 3D video datain a configured processing network, in accordance with an embodiment ofthe invention.

FIG. 12 is a flow chart that illustrates steps for scaling 3D video datafrom multiple sources in a configured processing network, in accordancewith an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor scaling 3D video. Various embodiments of the invention relate to anintegrated circuit (IC) comprising multiple devices that may beselectively interconnected to route and process 3D video data. The ICmay be operable to determine whether to scale the 3D video data beforethe 3D video data is captured to memory or after the captured 3D videodata is retrieved from the memory, and selectively interconnect one ormore of the devices based on the determination. The selectiveinterconnection may be based on input and output formats of the 3D videodata, and on a scaling factor. The input format may be a left-and-right(L/R) format or an over-and-under (O/U) format. Similarly, the outputformat may be a L/R format or an O/U format. The selectiveinterconnection may be based on input and output pixel rates of the 3Dvideo data. Moreover, the selective interconnection may be determined ona picture-by-picture basis.

FIG. 1 is a block diagram that illustrates a system-on-chip (SoC) thatis operable to handle 3D video data scaling, in accordance with anembodiment of the invention. Referring to FIG. 1, there is shown an SoC100, a host processor module 120, and a memory module 130. The SoC 100may comprise suitable logic, circuitry, code, and/or interfaces that maybe operable to receive and/or process one or more signals that comprisevideo content, including 3D video content. Examples of signalscomprising video content that may be received and processed by the SoC100 include, but need not be limited to, composite, blanking, and sync(CVBS) signals, separate video (S-video) signals, high-definitionmultimedia interface (HDMI) signals, component signals, personalcomputer (PC) signals, source input format (SIF) signals, YCrCb, andred, green, blue (RGB) signals. Such signals may be received by the SoC100 from one or more video sources communicatively coupled to the SoC100.

The SoC 100 may generate one or more output signals that may be providedto one or more output devices for display, reproduction, and/or storage.For example, output signals from the SoC 100 may be provided to displaydevices such as cathode ray tubes (CRTs), liquid crystal displays(LCDs), plasma display panels (PDPs), thin film transistor LCDs(TFT-LCDs), plasma, light emitting diode (LED), Organic LED (OLED), orother flatscreen display technology. The characteristics of the outputsignals, such as pixel rate and/or resolution, for example, may be basedon the type of output device to which those signals are to be provided.

The host processor module 120 may comprise suitable logic, circuitry,code, and/or interfaces that may be operable to control and/or configurethe operation of the SoC 100. For example, parameters and/or otherinformation, including but not limited to configuration data, may beprovided to the SoC 100 by the host processor module 120 at varioustimes during the operation of the SoC 100. The memory module 130 maycomprise suitable logic, circuitry, code, and/or interfaces that may beoperable to store information associated with the operation of the SoC100. For example, the memory module 130 may store intermediate valuesthat result during the processing of video data, including those valuesassociated with 3D video data processing.

The SoC 100 may comprise an interface module 102, a video processormodule 104, and a core processor module 106. The SoC 100 may beimplemented as a single integrated circuit comprising the componentslisted above. The interface module 102 may comprise suitable logic,circuitry, code, and/or interfaces that may be operable to receivemultiple signals that comprise video content. Similarly, the interfacemodule 102 may be operable to communicate one or more signals comprisingvideo content to output devices communicatively coupled to the SoC 100.

The video processor module 104 may comprise suitable logic, circuitry,code, and/or interfaces that may be operable to process video dataassociated with one or more signals received by the SoC 100. The videoprocessor module 104 may be operable to support multiple video dataformats, including multiple input formats and multiple output formatsfor 3D video data. The video processor module 104 may be operable toperform various types of operations on 3D video data, including but notlimited to format conversion and/or scaling. In some embodiments, whenthe video content comprises audio data, the video processor module 104,and/or another module in the SoC 100, may be operable to handle theaudio data.

The core processor module 106 may comprise suitable logic, circuitry,code, and/or interfaces that may be operable to control and/or configurethe operation of the SoC 100. For example, the core processor module 106may be operable to control and/or configure operations of the SoC 100that are associated with processing video content, including but notlimited to the processing of 3D video data. In this regard, the coreprocessor 106 may be operable to determine and/or calculate parametersassociated with the processing of 3D video data that may be utilized toconfigure and/or operate the video processor module 104. In someembodiments of the invention, the core processor module 106 may comprisememory (not shown) that may be utilized in connection with theoperations performed by the SoC 100. For example, the core processormodule 106 may comprise memory that may be utilized during 3D video dataprocessing by the video processor module 104.

In operation, the SoC 100 may receive one or more signals comprising 3Dvideo data through the interface module 102. When the 3D video datareceived in those signals is to be scaled, the video processor module104 and/or the core processor module 106 may be utilized to determinewhether to scale 3D video data in the video processor module 104 beforethe 3D video data is captured to memory through the video processormodule 104 or after the captured 3D video data is retrieved from thememory through the video processor module 104. The memory into which the3D video data is to be stored and from which it is to be subsequentlyretrieved may be a dynamic random access memory (DRAM) that may be partof the memory module 130 and/or of the core processor module 106, forexample.

At least a portion of the video processor module 104 may be configuredby the host processor module 120 and/or the core processor module 106according to the determined order in which to scale the 3D video data.Such order may be based on an input format of the 3D video data, anoutput format of the 3D video data, and on a scaling factor. Moreover,the order in which to scale the 3D video data may be determined on apicture-by-picture basis. That is, the order in which to scale the 3Dvideo data and the corresponding configuration of the video processormodule 104 may be carried out for each picture in a video sequence thatis received in the SoC. Once processed, the 3D video data may becommunicated to one or more output devices by the SoC 100.

As indicated above, the SoC 100 may be operable handle 3D video data inmultiple input formats and multiple output formats. The complexity ofthe SoC 100, however, may increase significantly the larger the numberof input and output formats supported. An approach that may simplify theSoC 100 and that may enable support for a large number of formats is toconvert an input format into one of a subset of formats supported by theSoC for processing and have the SoC 100 perform the processing of the 3Dvideo data in that format. Once the processing is completed, theprocessed 3D video data may be converted to the appropriate outputformat if such conversion is necessary.

FIGS. 2A-2E illustrate various input and output packing schemes for 3Dvideo data, in accordance with embodiments of the invention. Referringto FIG. 2A, there is shown a first packing scheme or first format 200for 3D video data and a second packing scheme or second format 210 for3D video data. Each of the first format 200 and the second format 210illustrates the arrangement of the left eye content (L) and the righteye content (R) in a 3D video picture. In this regard, a 3D videopicture may refer to a 3D video frame or a 3D video field in a videosequence, whichever is appropriate. The L and R in the first format 200are arranged in a side-by-side arrangement, which is typically referredto as a left-and-right (L/R) format. The L and R in the second format210 are arranged in a top-and-bottom arrangement, which is typicallyreferred to as an over-and-under (O/U) format. Another arrangement, onenot shown in FIG. 2A, may be one in which the L is in a first 3D videopicture and the R is in a second 3D video picture. Such arrangement maybe referred to as a sequential format because the 3D video pictures areprocessed sequentially.

Both the first format 200 and the second format 210 may be utilized bythe SoC 100 described above to process 3D video data and may be referredto as native formats of the SoC 100. When 3D video data is received inone of the multiple input formats supported by the SoC 100, the SoC 100may convert that input format to one of the first format 200 and thesecond format 210, if such conversion is necessary. The SoC 100 may thenprocess the 3D video data in a native format. Once the 3D video data isprocessed, the SoC 100 may convert the processed 3D video data into oneof the multiple output formats supported by the SoC 100, if suchconversion is necessary. The SoC 100 may also be operable to process 3Dvideo data in the sequential format, which is typically handled by theSoC 100 in a manner that is substantially similar to the handling of thesecond format 210.

Referring to FIG. 2B, there is shown a conversion mapping of certaininput formats 202 a, 204 a, and 206 a supported by the SoC 100 to thefirst format 200. For example, an L/R input format 202 a may beconverted to the first format 200, which is also an L/R format. Inanother example, a line interleaved input format 204 a may be convertedto the first format 200. In yet another example, a checkerboard inputformat 206 a may be converted to the first format 200. In each of thesescenarios, the SoC 100 may detect the type of input format associatedwith the 3D video data and may determine that the appropriate conversionof the detected input format is to the first format 200.

Referring to FIG. 2C, there is shown a conversion mapping of the firstformat 200 to certain output formats 202 b, 204 b, and 206 b supportedby the SoC 100. For example, the first format 200 may be converted to anL/R output format 202 b. In another example, the first format 200 may beconverted to a line interleaved output format 204 b. In yet anotherexample, the first format 200 may be converted to a checkerboard outputformat 206 b. In each of these scenarios, the SoC 100 may determine theappropriate type of output format to which the first format 200 is to beconverted.

Referring to FIG. 2D, there is shown a conversion mapping of certaininput formats 212 a, 214 a, and 216 a supported by the SoC 100 to thesecond format 210. For example, an O/U input format 212 a may beconverted to the second format 210, which is also an O/U format. Inanother example, an O/U ×2 input format 214 a may be converted to thesecond format 210. In yet another example, a multi-decode input format216 a may be converted to the second format 210. In each of thesescenarios, the SoC 100 may detect the type of input format associatedwith the 3D video data and may determine that the appropriate conversionof the detected input format is to the second format 210.

Referring to FIG. 2E, there is shown a conversion mapping of the secondformat 210 to certain output formats 212 b and 214 b supported by theSoC 100. For example, the second format 210 may be converted to an O/Uoutput format 212 b. In another example, the second format 210 may beconverted to an O/U x2 output format 214 b. In each of these scenarios,the SoC 100 may determine the appropriate type of output format to whichthe second format 210 is to be converted.

The conversion operations supported by the SoC 100 may also compriseconverting from the first format 200 to the second format 210 andconverting from the second format 210 to the first format 200. In thismanner, 3D video data may be received in any one of multiple inputformats, such as the input formats 202 a, 204 a, 206 a, 212 a, 214 a,and 216 a (FIGS. 2B and 2D). Accordingly, resulting processed 3D videodata may be generated in any one of multiple output formats, such as theoutput formats 202 b, 204 b, 206 b, 212 b, and 214 b (FIGS. 2C and 2E).

The various input formats and output formats described above withrespect to FIGS. 2A-2E are provided by way of illustration and not oflimitation. The SoC 100 may support additional input formats that may beconverted to a native format such as the first format 200, the secondformat 210, and the sequential format. Similarly, the SoC may supportadditional output formats to which a native format may be converted.

FIGS. 3A-3C are block diagrams that illustrate a processing network thatis operable to scale 3D video data, in accordance with embodiments ofthe invention. Referring to FIG. 3A, there is shown a processing network300 that may be part of the video processor module 104 in the SoC 100,for example. The processing network 300 may comprise suitable logic,circuitry, code, and/or interfaces that may be operable to route andprocess video data, including 3D video data. In this regard, theprocessing network 300 may comprise multiple devices, components,modules, blocks, circuits, or the like, that may be selectivelyinterconnected to enable the routing and processing of video data. Thevarious devices, components, modules, blocks, circuits, or the like inthe processing network 300 may be dynamically configured and/ordynamically interconnected during the operation of the SoC 100 throughone or more signals generated by the core processor module 106 and/or bythe host processor module 120. In this regard, the configuration and/orthe selective interconnection of various portions of the processingnetwork 300 may be performed on a picture-by-picture basis when such anapproach is appropriate to handle varying characteristics of the videodata.

In the embodiment of the invention described in FIG. 3A, the processingnetwork 300 may comprise an MPEG feeder (MFD) module 302, multiple videofeeder (VFD) modules 304, an HDMI module 306, crossbar modules 310 a and310 b, multiple scaler (SCL) modules 308, a motion-adaptive deinterlacer(MAD) module 312, a digital noise reduction (DNR) module 314, multiplecapture (CAP) modules 320, and two compositor (CMP) modules 322. Each ofthe above-listed components may be operable to handle video data,including 3D video data. The references to a memory (not shown) in FIG.3A may be associated with a DRAM utilized by the processing network 300to handle storage of video data during various operations. Such DRAM maybe part of the memory module 130 described above with respect to FIG. 1.In some instances, the DRAM may be part of memory embedded in the SoC100. The references to a video encoder (not shown) in FIG. 3A may beassociated with hardware and/or software in the SoC 100 that may beutilized after the processing network 300 to further process video datafor communication to an output device, such as a display device, forexample.

Each of the crossbar modules 310 a and 310 b may comprise multiple inputports and multiple output ports. The crossbar modules 310 a and 310 bmay be configured such that any one of the input ports may be connectedto one or more of the output ports. The crossbar modules 310 a and 310 bmay enable pass-through connections 316 between one or more output portsof the crossbar module 310 a and corresponding input ports of thecrossbar module 310 b. Moreover, the crossbar modules 310 a and 310 bmay enable feedback connections 318 between one or more output ports ofthe crossbar module 310 b and corresponding input ports of the crossbarmodule 310 a. The configuration of the crossbar modules 310 a and/or 310b may result in one or more processing paths being configured within theprocessing network 300 in accordance with the manner and/or order inwhich video data is to be processed.

The MFD module 302 may be operable to read video data from memory andprovide such video data to the crossbar module 310 a. The video dataread by the MFD module 302 may have been stored in memory after beinggenerated by an MPEG encoder (not shown). Each VFD module 304 may beoperable to read video data from memory and provide such video data tothe crossbar module 310. The video data read by the VFD module 304 mayhave been stored in memory in connection with one or more operationsand/or processes associated with the processing network 300. The HDMImodule 306 may be operable to provide a live feed of high-definitionvideo data to the crossbar module 310 a. The HDMI module 306 maycomprise a buffer (not shown) that may enable the HDMI module 306 toreceive the live feed at one data rate and provide the live feed to thecrossbar module 310 a at another data rate.

Each SCL module 308 may be operable to scale video data received fromthe crossbar module 310 a and provide the scaled video data to thecrossbar module 310 b. The MAD module 312 may be operable to performmotion-adaptive deinterlacing operations on interlaced video datareceived from the crossbar module 310 a, including operations related toinverse telecine (IT), and provide progressive video data to thecrossbar module 310 b. The DNR module 314 may be operable to performartifact reduction operations on video data received from the crossbarmodule 310 a, including block noise reduction and mosquito noisereduction, for example, and provide the noise-reduced video data to thecrossbar module 310 b. In some embodiments of the invention, theoperations performed by the DNR module 314 may be utilized before theoperations of the MAD module 312 and/or the operations of the SCL module308.

Each CAP module 320 may be operable to capture video data from thecrossbar module 310 b and store the captured video data in memory. EachCMP module 322 may be operable to blend or combine video data receivedfrom the crossbar module 310 b with graphics data. For example, FIG. 3Ashows one CMP module 322 being provided with a graphics feed Gfxa thatis blended by the CMP module 322 with video data received from thecrossbar module 310 b before the combination is communicated to a videoencoder. Similarly, another CMP module 322 is provided with a graphicsfeed Gfxb that is blended by the CMP module 322 with video data receivedfrom the crossbar module 310 b before the combination is communicated toa video encoder.

Referring to FIG. 3B, there is shown the SCL module 308 in a firstconfiguration that may be utilized when the 3D video data scalingcomprises scaling down horizontally. In this configuration, the SCLmodule 308 may comprise a horizontal scaler (HSCL) module 330, which maybe configured to operate first and handles the horizontal scaling (sx)of the video data, and a vertical scaler (VSCL) module 332, which may beconfigured to operate after the horizontal scaling and handles thevertical scaling (sy) of the video data. The overall scaling of the SCLmodule 308 in this configuration may be given by the product sx·sy. Theinput pixel rate of the SCL module 308 at node “in” is SCL_(in), theoutput pixel rate of the HSCL module 330 at node “H” is SCL_(H), and theoutput pixel rate of the VSCL module 332 at node “V” is SCL_(V), whichis the same as the output pixel rate of the SCL module 308 at node“out”, SCL_(out).

Referring to FIG. 3C, there is shown the SCL module 308 in a secondconfiguration that may be utilized when the 3D video data scalingcomprises scaling up horizontally. In this configuration, the VSCLmodule 332 may be configured to operate first and the HSCL module 330may be configured to operate after the VSCL module 332. The overallscaling of the SCL module 308 in this configuration may be given by theproduct sy·sx. The input pixel rate of the SCL module 308 at node “in”is SCL_(in), the output pixel rate of the VSCL module 332 at node “V” isSCL_(V), and the output pixel rate of the HSCL module 330 at node “H” isSCL_(H), which is the same as the output pixel rate of the SCL module308 at node “out”, SCL_(out).

By configuring the processing network 300 and/or one or more of the SCLmodules 308, the processing network 300 may be utilized to scale and/orprocess 3D video data received by the SoC 100 in any one of the multipleinput formats supported by the SoC 100, such as those described abovewith respect to FIGS. 2B and 2D, for example. Similarly, the scaledand/or processed 3D video data generated by the configured processingnetwork 300 and/or one or more SCL modules 308 may be converted, ifnecessary, to any one of the multiple output formats supported by theSoC 100, such as those described above with respect to FIGS. 2C and 2E,for example.

FIGS. 4A and 4B illustrate format-related variables for L/R format andO/U format, respectively, in accordance with embodiments of theinvention. Referring to FIG. 4A, there is shown a 3D video data picture400 that illustrates some of the variables associated with aside-by-side or left-and-right arrangement. FIG. 4B shows a 3D videodata picture 410 that illustrates the same variables when associatedwith a top-and-bottom or over-and-under arrangement. For example, whenthe picture 400 or the picture 410 is associated with an input format,such as before the 3D video data is scaled and/or processed by theprocessing network 300, the variables may be described as follows:xtot=ixtot is the total width of the picture, ytot=iytot is the totalheight of the picture, xact=ixact is the active width of the picture,yact=iyact is the active height of the picture, x=ix is the width of thearea of the picture that is to be cropped and displayed, and y=iy is theheight of the area of the picture that is to be cropped and displayed.

When the picture 400 or the picture 410 is associated with an outputformat, such as after the 3D video data is scaled and/or processed bythe processing network 300, the variables may be described as follows:xtot=oxtot is the total width of the picture, ytot=oytot is the totalheight of the picture, xact=oxact is the active width of the picture,yact=oyact is the active height of the picture, x=ox is the width of thearea on the display that the input content is to be displayed, and y=oyis the height of the area on the display that the input content is to bedisplayed.

Based on the variables described in FIGS. 4A and 4B, a 3D video picturemay be scaled up horizontally when ox>ix, may be scaled downhorizontally when ox<ix, may be scaled up vertically when oy>iy, and maybe scaled down vertically when oy<iy.

When 3D video data received by the SoC 100 is scaled utilizing theprocessing network 300, the order in which the scaling of the 3D videodata occurs with respect to the operations provided by the CAP module320 and the VFD module 304 may depend on the characteristics of theinput format of the 3D video data, the output format of the 3D videodata, and the scaling that is to take place. In this regard, there maybe bandwidth considerations when determining the appropriate order inwhich to carry out the scaling of the 3D video data, and consequently,the appropriate configuration of the processing network 300. Below areprovided various scenarios that describe the selection of the order orpositioning of the scaling operation in a sequence of operations thatmay be performed on 3D video data by the processing network 300.

FIGS. 5A and 5B illustrate configurations of the processing network 300when scaling 3D video data from an L/R input format to an L/R outputformat, in accordance with embodiments of the invention. Referring toFIG. 5A, there is shown a first configuration 500 of the processingnetwork 300 that may be utilized when an L/R input format and an L/Routput format are being considered and the 3D video data scalingoperation is determined to occur before the capture operation. The firstconfiguration 500 may refer to a particular interconnection and/oroperation of several of the modules in the processing network 300. Forexample, in the first configuration 500, the 3D video data may beprovided to one of the SCL modules 308 from the MFD module 302 or fromthe HDMI module 306 by the appropriate configuration of the crossbarmodule 310 a. The output of the SCL module 308 may be provided to one ofthe CAP modules 320 by the appropriate configuration of the crossbarmodule 310 b. The scaled 3D video data may be captured by the CAP module320 and may be stored in a memory 502. The memory 502 may be a DRAMmemory, for example. One of the VFD modules 304 may retrieve the scaledand captured 3D video data from the memory 502 and may provide theretrieved 3D video data to one of the CMP modules 322 through thepass-through connections 316 between the crossbar modules 310 a and 310b. The CMP module 322 may subsequently communicate the 3D video data toa video encoder.

In the first configuration 500, the pixel rate at node “A”, p_rate_(A),is the same as the input pixel rate of the SCL module 308, SCL_(in). Theoutput pixel rate of the SCL module 308 isSCL_(out)=SCL_(in)·sx·sy=p_rate_(A)·sx·sy. Moreover, the pixel rate atnode “C”, p_rate_(C), is associated with the output characteristics ofthe 3D video data.

With respect to the CAP module 320 in the first configuration 500, thereal time scheduling, cap_rts₁, is based on the number of requests for aline of data, n_req, and a time available for all requests, t_n_reqs.With L and R captured separately, these variables may be determined asfollows:

$\begin{matrix}{{{n\_ req} = \left\lceil \frac{ox}{N_{C}} \right\rceil},} & (1) \\\begin{matrix}{{{t\_ n}{\_ req}} = \frac{ox}{S\; C\; L_{out}}} \\{= \frac{ox}{{p\_ rate}_{A} \cdot {sx} \cdot {sy}}} \\{{= {\frac{ix}{{p\_ rate}_{A}} \cdot \frac{1}{sy}}},}\end{matrix} & (2) \\{{{cap\_ rts}_{1} = {\frac{n\_ req}{{t\_ n}{\_ req}} = {\left( {\frac{ix}{{p\_ rate}_{A}} \cdot \frac{1}{sy}} \right)/\left\lceil \frac{ox}{N_{C}} \right\rceil}}},} & (3)\end{matrix}$

where ox is the width of the area on the display that the input contentis to be displayed as indicated above with respect to FIGS. 4A and 4B,and N_(c) is the burst size of the CAP module 320 in number of pixels.

With respect to the VFD module 304 in the first configuration 500, thereal time scheduling, vfd_rts₁, is based on the number of requests for aline of data, n_req, and a time available for all requests, t n_reqs.With L and R captured separately, these variables may be determined asfollows:

$\begin{matrix}{{{n\_ req} = \left\lceil \frac{ox}{N_{V}} \right\rceil},} & (4) \\{{{{t\_ n}{\_ req}} = \frac{ox}{{p\_ rate}_{C}}},} & (5) \\{{{vfd\_ rts}_{1} = {\frac{n\_ req}{{t\_ n}{\_ req}} = {\frac{ox}{{p\_ rate}_{C}}/\left\lceil \frac{ox}{N_{V}} \right\rceil}}},} & (6)\end{matrix}$

where N_(V) is the burst size of the VFD module 304 in number of pixels.

Referring to FIG. 5B, there is shown a second configuration 510 of theprocessing network 300 that may be utilized when an L/R input format andan L/R output format are being considered and the 3D video data scalingoperation is determined to occur after the captured 3D video data isretrieved from memory. The second configuration 510 may refer to aparticular interconnection and/or operation of several of the modules inthe processing network 300. For example, in the second configuration510, the 3D video data may be provided to one of the CAP modules 320from the MFD module 302 or from the HDMI module 306 through thepass-through connections 316 between the crossbar modules 310 a and 310b. The 3D video data may be captured by the CAP module 320 and may bestored in the memory 502. One of the VFD modules 304 may retrieve thecaptured 3D video data from the memory 502 and may provide the retrieved3D video data to one of the SCL modules 308 by the appropriateconfiguration of the crossbar module 310 a. The output of the SCL module308 may be provided to one of the CMP modules 322 by the appropriateconfiguration of the crossbar module 310 b. The CMP module 322 maysubsequently communicate the 3D video data to a video encoder.

In the second configuration 510, the pixel rate at node “C”, p_rate_(C),may be the same as the output pixel rate of the SCL module 308,SCL_(out). The input pixel rate of the SCL module 308 may beSCL_(in)=SCL_(out)/(sx·sy)=p_rate_(C)/(sx·sy). Moreover, the pixel rateat node “A”, p_rate_(A), may be associated with the inputcharacteristics of the 3D video data.

With respect to the CAP module 320 in the second configuration 510, thereal time scheduling, cap_rts₂, is based on the number of requests for aline of data, nreq, and a time available for all requests, t n_reqs.With L and R captured separately, these variables may be determined asfollows:

$\begin{matrix}{{{n\_ req} = \left\lceil \frac{ix}{N_{C}} \right\rceil},} & (7) \\{{{{t\_ n}{\_ req}} = \frac{ix}{{p\_ rate}_{A}}},} & (8) \\{{{cap\_ rts}_{2} = {\frac{{t\_ n}{\_ req}}{n\_ req} = {\frac{ix}{{p\_ rate}_{A}}/\left\lceil \frac{ix}{N_{C}} \right\rceil}}},} & (9)\end{matrix}$

where ix is the width of the area of the picture that is to be croppedand displayed as indicated above with respect to FIGS. 4A and 4B.

With respect to the VFD module 304 in the second configuration 510, thereal time scheduling, vfd_rts₂, is based on the number of requests for aline of data, n_req, and a time available for all requests, t_n_reqs.With L and R captured separately, these variables may be determined asfollows:

$\begin{matrix}{{{n\_ req} = \left\lceil \frac{ix}{N_{V}} \right\rceil},} & (10) \\{{{{t\_ n}{\_ req}} = {\frac{ix}{S\; C\; L_{i\; n}} = {\frac{ix}{{p\_ rate}_{C}/\left( {{sx} \cdot {sy}} \right)} = \frac{{ox} \cdot {sy}}{{p\_ rate}_{C}}}}},} & (11) \\{{vfd\_ rts}_{2} = {\frac{{t\_ n}{\_ req}}{n\_ req} = {\frac{ox}{{p\_ rate}_{C}} \cdot {{sy}/{\left\lceil \frac{ix}{N_{V}} \right\rceil.}}}}} & (12)\end{matrix}$

A decision or selection as to whether to perform the scaling operationbefore capture, as in the first configuration 500, or after the captureddata is retrieved from memory, as in the second configuration 510, maybe based on the bandwidths associated with both scenarios. For the casewhen the burst size of the CAP module 320 and the burst size of the VFDmodule 304 are the same (i.e., N_(c)=N_(v)=N), the bandwidthcalculations may be determined as follows:

$\begin{matrix}{{{{BW}\; 1} = {{{cap\_ rts}_{1} + {vfd\_ rts}_{1}} = {\left( {{\frac{ix}{{p\_ rate}_{A}} \cdot \frac{1}{sy}} + \frac{ox}{{p\_ rate}_{C}}} \right)/\left\lceil \frac{ox}{N} \right\rceil}}},} & (13) \\{{{{BW}\; 2} = {{{cap\_ rts}_{2} + {vfd\_ rts}_{2}} = {\left( {\frac{ix}{{p\_ rate}_{A}} + {\frac{ox}{{p\_ rate}_{C}} \cdot {sy}}} \right)/\left\lceil \frac{ix}{N} \right\rceil}}},} & (14) \\{{\lambda = {\frac{{BW}\; 2}{{BW}\; 1} = {\frac{\left\lceil {{ox}/N} \right\rceil}{\left\lceil {{ix}/N} \right\rceil} \cdot {sy}}}},} & (15)\end{matrix}$

where BW1 is the bandwidth associated with the first configuration 500,BW2 is the bandwidth associated with the second configuration 510, and λis the ratio of the two bandwidths. When λ<1, the SCL module 308 is tobe positioned before the CAP module 320, as in the first configuration500, and when λ>1, the SCL module 308 is to be positioned after the VFDmodule 304, as in the second configuration 510.

FIGS. 6A and 6B illustrate configurations of the processing network 300when scaling 3D video data from an L/R input format to an O/U outputformat, in accordance with embodiments of the invention. Referring toFIG. 6A, there is shown a third configuration 600 of the processingnetwork 300 that may be utilized when an L/R input format and an O/Uoutput format are being considered and the 3D video data scalingoperation is determined to occur before the capture operation. The thirdconfiguration 600 may refer to a particular interconnection and/oroperation of several of the modules in the processing network 300. Inthe third configuration 600, the arrangement of the processing network300 may be similar to that of the first configuration 500 in FIG. 5A.That is, the 3D video data may be provided to one of the SCL modules 308from the MFD module 302 or from the HDMI module 306 by the appropriateconfiguration of the crossbar module 310 a. The output of the SCL module308 may be provided to one of the CAP modules 320 by the appropriateconfiguration of the crossbar module 310 b. The scaled 3D video data maybe captured by the CAP module 320 and may be stored in the memory 502.One of the VFD modules 304 may retrieve the scaled and captured 3D videodata from the memory 502 and may provide the retrieved 3D video data toone of the CMP modules 322 through the pass-through connections 316between the crossbar modules 310 a and 310 b. The CMP module 322 maysubsequently communicate the 3D video data to a video encoder.

With respect to the CAP module 320 in the third configuration 600, thereal time scheduling, cap_rts₃, may be determined as follows:

$\begin{matrix}{{cap\_ rts}_{3} = {\left( {\frac{ix}{{p\_ rate}_{A}} \cdot \frac{1}{sy}} \right)/{\left\lceil \frac{ox}{N_{C}} \right\rceil.}}} & (16)\end{matrix}$

With respect to the VFD module 304 in the third configuration 600, thereal time scheduling, vfd_rts₃, may be determined as follows:

$\begin{matrix}{{{vfd\_ rts}_{3} = {\frac{ox}{{p\_ rate}_{D}}/\left\lceil \frac{ox}{N_{V}} \right\rceil}},} & (17)\end{matrix}$

where the pixel rate at node “D”, p_rate_(D), may be associated with theoutput characteristics of the 3D video data.

Referring to FIG. 6B, there is shown a fourth configuration 610 of theprocessing network 300 that may be utilized when an L/R input format andan O/U output format are being considered and the 3D video data scalingoperation is determined to occur after the captured 3D video data isretrieved from memory. The fourth configuration 610 may refer to aparticular interconnection and/or operation of several of the modules inthe processing network 300. In the fourth configuration 610, thearrangement of the processing network 300 may be similar to that of thesecond configuration 510 in FIG. 5B. That is, the 3D video data may beprovided to one of the CAP modules 320 from the MFD module 302 or fromthe HDMI module 306 through the pass-through connections 316 between thecrossbar modules 310 a and 310 b. The 3D video data may be captured bythe CAP module 320 and may be stored in the memory 502. One of the VFDmodules 304 may retrieve the captured 3D video data from the memory 502and may provide the retrieved 3D video data to one of the SCL modules308 by the appropriate configuration of the crossbar module 310 a. Theoutput of the SCL module 308 may be provided to one of the CMP modules322 by the appropriate configuration of the crossbar module 310 b. TheCMP module 322 may subsequently communicate the 3D video data to a videoencoder.

With respect to the CAP module 320 in the fourth configuration 610, thereal time scheduling, cap_rts₄, may be determined as follows:

$\begin{matrix}{{{cap\_ rts}_{4} = {\frac{ix}{{p\_ rate}_{A}}/\left\lceil \frac{ix}{N_{C}} \right\rceil}},} & (18)\end{matrix}$

With respect to the VFD module 304 in the fourth configuration 610, thereal time scheduling, vfd_rts₄, may be determined as follows:

$\begin{matrix}{{{vfd\_ rts}_{4} = {\frac{ox}{{p\_ rate}_{D}} \cdot {{sy}/\left\lceil \frac{ix}{N_{V}} \right\rceil}}},} & (19)\end{matrix}$

where the pixel rate at node “D”, p_rate_(D), may be the same as theoutput pixel rate of the SCL module 308, SCL_(out).

A decision or selection as to whether to perform the scaling operationbefore capture, as in the third configuration 600, or after the captureddata is retrieved from memory, as in the fourth configuration 610, maybe based on the bandwidths associated with both scenarios. For the casewhen the burst size of the CAP module 320 and the burst size of the VFDmodule 304 are the same (i.e., N_(C)=N_(V)=N), the following ratio maybe determined:

$\begin{matrix}{\lambda = {\frac{{BW}\; 2}{{BW}\; 1} = {\frac{\left\lceil {{ox}/N} \right\rceil}{\left\lceil {{ix}/N} \right\rceil} \cdot {{sy}.}}}} & (22)\end{matrix}$

where BW1 is the bandwidth associated with the third configuration 600,BW2 is the bandwidth associated with the fourth configuration 610, and λis the ratio of the two bandwidths. When λ<1, the SCL module 308 is tobe positioned before the CAP module 320, as in the third configuration600, and when λ>1, the SCL module 308 is to be positioned after the VFDmodule 304, as in the fourth configuration 610.

FIGS. 7A and 7B illustrate configurations of the processing network 300when scaling 3D video data from an O/U input format to an L/R outputformat, in accordance with embodiments of the invention. Referring toFIG. 7A, there is shown a fifth configuration 700 of the processingnetwork 300 that may be utilized when an O/U input format and an L/Routput format are being considered and the 3D video data scalingoperation is determined to occur before the capture operation. The fifthconfiguration 700 may refer to a particular interconnection and/oroperation of several of the modules in the processing network 300. Inthis configuration, the arrangement of the processing network 300 may besimilar to that of the first configuration 500 in FIG. 5A.

With respect to the CAP module 320 in the fifth configuration 700, thereal time scheduling, cap may be determined as follows:

$\begin{matrix}{{{cap\_ rts}_{5} = {\left( {\frac{ix}{{p\_ rate}_{B}} \cdot \frac{1}{sy}} \right)/\left\lceil \frac{ox}{N_{C}} \right\rceil}},} & (23)\end{matrix}$

where the pixel rate at node “B”, p_rate_(B), may be the same as theinput pixel rate of the SCL module 308, SCL_(in).

With respect to the VFD module 304 in the fifth configuration 700, thereal time scheduling, vfd_rts₅, may be determined as follows:

$\begin{matrix}{{vfd\_ rts}_{5} = {\frac{ox}{{p\_ rate}_{C}}/{\left\lceil \frac{ox}{N_{V}} \right\rceil.}}} & (24)\end{matrix}$

Referring to FIG. 7B, there is shown a sixth configuration 710 of theprocessing network 300 that may be utilized when an O/U input format andan L/R output format are being considered and the 3D video data scalingoperation is determined to occur after the captured 3D video data isretrieved from memory. The sixth configuration 710 may refer to aparticular interconnection and/or operation of several of the modules inthe processing network 300. In this configuration, the arrangement ofthe processing network 300 may be similar to that of the secondconfiguration 510 in FIG. 5B.

With respect to the CAP module 320 in the sixth configuration 710, thereal time scheduling, cap_rts_(s), may be determined as follows:

$\begin{matrix}{{{cap\_ rts}_{6} = {\frac{ix}{{p\_ rate}_{B}}/\left\lceil \frac{ix}{N_{C}} \right\rceil}},} & (25)\end{matrix}$

where the pixel rate at node “B”, p_rate_(B), may be associated with theinput characteristics of the 3D video data.

With respect to the VFD module 304 in the sixth configuration 710, thereal time scheduling, vfd_rts_(s), may be determined as follows:

$\begin{matrix}{{vfd\_ rts}_{6} = {\frac{ox}{{p\_ rate}_{C}} \cdot {{sy}/{\left\lceil \frac{ix}{N_{V}} \right\rceil.}}}} & (26)\end{matrix}$

A decision or selection as to whether to perform the scaling operationbefore capture, as in the fifth configuration 700, or after the captureddata is retrieved from memory, as in the sixth configuration 710, may bebased on the bandwidths associated with both scenarios. For the casewhen the burst size of the CAP module 320 and the burst size of the VFDmodule 304 are the same (i.e., N_(c)=N_(v)=N), the following ratio maybe determined:

$\begin{matrix}{{\lambda = {\frac{{BW}\; 2}{{BW}\; 1} = {\frac{\left\lceil {{ox}/N} \right\rceil}{\left\lceil {{ix}/N} \right\rceil} \cdot {sy}}}},} & (27)\end{matrix}$

where BW1 is the bandwidth associated with the fifth configuration 700,BW2 is the bandwidth associated with the sixth configuration 710, and λis the ratio of the two bandwidths. When λ<1, the SCL module 308 is tobe positioned before the CAP module 320, as in the fifth configuration700, and when λ>1, the SCL module 308 is to be positioned after the VFDmodule 304, as in the sixth configuration 710.

FIGS. 8A and 8B illustrate configurations of the processing network 300when scaling 3D video data from an O/U input format to an O/U outputformat, in accordance with embodiments of the invention. Referring toFIG. 8A, there is shown a seventh configuration 800 of the processingnetwork 300 that may be utilized when an O/U input format and an O/Uoutput format are being considered and the 3D video data scalingoperation is determined to occur before the capture operation. Theseventh configuration 800 may refer to a particular interconnectionand/or operation of several of the modules in the processing network300. In this configuration, the arrangement of the processing network300 may be similar to that of the first configuration 500 in FIG. 5A.

With respect to the CAP module 320 in the seventh configuration 800, thereal time scheduling, cap may be determined as follows:

$\begin{matrix}{{cap\_ rts}_{7} = {\left( {\frac{ix}{{p\_ rate}_{B}} \cdot \frac{1}{sy}} \right)/{\left\lceil \frac{ox}{N_{C}} \right\rceil.}}} & (28)\end{matrix}$

With respect to the VFD module 304 in the seventh configuration 800, thereal time scheduling, vfd_rts₇, may be determined as follows:

$\begin{matrix}{{vfd\_ rts}_{7} = {\frac{ox}{{p\_ rate}_{D}}/{\left\lceil \frac{ox}{N_{V}} \right\rceil.}}} & (29)\end{matrix}$

Referring to FIG. 8B, there is shown an eighth configuration 810 of theprocessing network 300 that may be utilized when an O/U input format andan O/U output format are being considered and the 3D video data scalingoperation is determined to occur after the captured 3D video data isretrieved from memory. The eighth configuration 810 may refer to aparticular interconnection and/or operation of several of the modules inthe processing network 300. In this configuration, the arrangement ofthe processing network 300 may be similar to that of the secondconfiguration 510 in FIG. 5B.

With respect to the CAP module 320 in the eighth configuration 810, thereal time scheduling, cap may be determined as follows:

$\begin{matrix}{{cap\_ rts}_{8} = {\frac{ix}{{p\_ rate}_{B}}/{\left\lceil \frac{ix}{N_{C}} \right\rceil.}}} & (30)\end{matrix}$

With respect to the VFD module 304 in the eighth configuration 810, thereal time scheduling, vfd_rts_(s), may be determined as follows:

$\begin{matrix}{{vfd\_ rts}_{8} = {\frac{ox}{{p\_ rate}_{D}} \cdot {{sy}/{\left\lceil \frac{ix}{N_{V}} \right\rceil.}}}} & (31)\end{matrix}$

A decision or selection as to whether to perform the scaling operationbefore capture, as in the seventh configuration 800, or after thecaptured data is retrieved from memory, as in the eighth configuration810, may be based on the bandwidths associated with both scenarios. Forthe case when the burst size of the CAP module 320 and the burst size ofthe VFD module 304 are the same (i.e., N_(c)=N_(v)=N), the followingratio may be determined:

$\begin{matrix}{{\lambda = {\frac{{BW}\; 2}{{BW}\; 1} = {\frac{\left\lceil {{ox}/N} \right\rceil}{\left\lceil {{ix}/N} \right\rceil} \cdot {sy}}}},} & (32)\end{matrix}$

where BW1 is the bandwidth associated with the seventh configuration800, BW2 is the bandwidth associated with the eighth configuration 810,and λ is the ratio of the two bandwidths. When λ<1, the SCL module 308is to be positioned before the CAP module 320, as in the seventhconfiguration 800, and when λ>1, the SCL module 308 is to be positionedafter the VFD module 304, as in the eighth configuration 810.

FIG. 9 is a diagram that illustrates an example of scaling on thecapture side when the 3D video has a 1080 progressive (1080p) O/U inputformat and a 720p L/R output format, in accordance with an embodiment ofthe invention. Referring to FIG. 9, the example shown corresponds to thefifth configuration 700 described above with respect to FIG. 7A. In thisexample, an input picture 900, which is formatted as 1080p O/U 3D videodata, is provided to the processing network 300 for scaling and/orprocessing. The input picture 900 is scaled by a scaling operation 910that is performed by, for example, one of the SCL modules 308 shown inFIG. 3A. A scaled picture 920 is then captured to memory by a captureoperation 930 performed by, for example, one of the CAP modules 320shown in FIG. 3A. The captured picture is retrieved from memory througha capture retrieval operation 940 performed by, for example, one of theVFD modules 304 shown in FIG. 3A. The retrieval of the captured picture,that is, the manner in which the 3D video data is read from the memory,is performed such that an output picture 950 is generated having a 720pL/R format.

FIGS. 10A and 10B are block diagrams that illustrate the order in whichadditional video processing operations may be performed in theprocessing network 300 when configured for scaling 3D video data, inaccordance with embodiments of the invention. Referring to FIG. 10A,there is shown a ninth configuration 1000 of the processing network 300in which the location of the SCL module 308 is before the CAP module320. The ninth configuration 1000 may refer to a particularinterconnection and/or operation of several of the modules in theprocessing network 300. In this configuration, additional processingcores or operations may be performed on the 3D video data. For example,a first core (P1) module 1002 may be positioned before the SCL module308, while a second core (P2) module 1004 may be positioned after theSCL module 308. Moreover, a third core (P3) module 1006 may bepositioned after the VFD module 304. The various core modules describedherein may refer to processing modules in the processing network 300such as the MAD module 312 and/or the DNR module 314. Other modules notshown in FIG. 3A, but that may be included in the processing network300, may also be utilized as core modules in the ninth configuration1000.

Referring to FIG. 10B, there is shown a tenth configuration 1010 of theprocessing network 300 in which the location of the SCL module 308 isafter the VFD module 304. The tenth configuration 1010 may refer to aparticular interconnection and/or operation of several of the modules inthe processing network 300. In this configuration, additional processingcores or operations may be performed on the 3D video data. For example,the P1 module 1002 may be positioned before the CAP module 320. The P2module 1004 may be positioned after the VFD module 304 and before theSCL module 308. Moreover, the P3 module 1006 may be positioned after theSCL module 308. As indicated above, the various core modules describedherein may refer to processing modules in the processing network 300such as the MAD module 312 and/or the DNR module 314. Other modules notshown in FIG. 3A, but that may be included in the processing network300, may also be utilized as core modules in the tenth configuration1010.

FIG. 11 is a flow chart that illustrates steps for scaling 3D video datain the configured processing network 300, in accordance with anembodiment of the invention. Referring to FIG. 11, there is shown a flowchart 1100 in which, at step 1110, the video processor module 104 in theSoC 100 may receive 3D video data from a source of such data. At step1120, the video processor module 104 and/or the host processor module120 may determine whether to scale the 3D video data received beforecapture to memory through the video processor module 104 or aftercapture to memory and subsequent retrieval from memory through the videoprocessor module 104.

At step 1130, the video processor module 104 and/or the host processormodule 120 may configure a portion of the video processor module 104comprising a processing network, such as the processing network 300shown in FIG. 3A. The configuration may be based on the order orpositioning determined in step 1120 regarding the scaling of the 3Dvideo data. At step 1140, the 3D video data may be scaled by theconfigured processing network in the video processor module 104.

FIG. 12 is a flow chart that illustrates steps for scaling 3D video datafrom multiple sources in the configured processing network 300, inaccordance with an embodiment of the invention. Referring to FIG. 12,there is shown a flow chart 1200 in which, at step 1210, the videoprocessor module 104 in the SoC 100 may receive 3D video data frommultiple sources of such data. At step 1220, the video processor module104 and/or the host processor module 120 may determine, for each of thesources, whether to scale the 3D video data received before capture tomemory through the video processor module 104 or after capture to memoryand subsequent retrieval from memory through the video processor module104.

At step 1230, the video processor module 104 and/or the host processormodule 120 may configure a portion of the video processor module 104comprising a processing network, such as the processing network 300shown in FIG. 3A. The configuration may be based on the order orpositioning determined in step 1220 regarding the scaling of the 3Dvideo data for each of the sources. In this regard, the processingnetwork may be configured to have multiple paths for processing the 3Dvideo data from the various sources of such data. At step 1240, the 3Dvideo data from each source may be scaled by the configured processingnetwork in the video processor module 104.

Various embodiments of the invention relate to an integrated circuit,such as the SoC 100 described above with respect to FIG. 1, for example,which may be operable to selectively route and process 3D video data.For example, the processing network 300 described above with respect toFIG. 3A may be utilized in the SoC 100 to route and process 3D videodata. The integrated circuit may comprise multiple devices, such as thevarious modules in the processing network 300, for example, which may beoperable to be selectively interconnected to enable the routing and theprocessing of 3D video data. The integrated circuit may be operable todetermine whether to scale the 3D video data before the 3D video data iscaptured to memory or after the captured 3D video data is retrieved fromthe memory. Moreover, the integrated circuit may be operable toselectively interconnect one or more of the multiple devices based onthe determination.

The integrated circuit may be operable to determine the selectiveinterconnection of the one or more of devices based on an input formatof the 3D video data, an output format of the 3D video data, and ascaling factor. The input format of the 3D video data may be a L/R inputformat or an O/U input format and the output format of the 3D video datamay be a L/R output format or an O/U output format. The integratedcircuit may be operable to determine the selective interconnection ofthe one or more devices based on an input pixel rate of the 3D videodata and on an output pixel rate of the 3D video data. The integratedcircuit may be operable to determine the selective interconnection ofthe one or more devices on a picture-by-picture basis.

The selectively interconnected devices in the integrated circuit may beoperable to horizontally scale the 3D video data and to vertically scalethe 3D video data. Moreover, the selectively interconnected devices inthe integrated circuit may be operable to perform one or more operationson the 3D video data before the 3D video data is scaled, after the 3Dvideo data is scale, or both.

In another embodiment of the invention, a non-transitory machine and/orcomputer readable storage and/or medium may be provided, having storedthereon a machine code and/or a computer program having at least onecode section executable by a machine and/or a computer, thereby causingthe machine and/or computer to perform the steps as described herein forscaling 3D video.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputer system or in a distributed fashion where different elements maybe spread across several interconnected computer systems. Any kind ofcomputer system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A method, comprising: in an integrated circuit operable toselectively route and process 3D video data, the integrated circuitcomprising a plurality of devices that are operable to be selectivelyinterconnected to enable the routing and the processing: determiningwhether to scale the 3D video data before the 3D video data is capturedto memory or after the captured 3D video data is retrieved from thememory; and selectively interconnecting one or more of the plurality ofdevices based on the determination.
 2. The method of claim 1, whereinthe selective interconnection of the one or more of the plurality ofdevices in the integrated circuit is determined based on an input formatof the 3D video data, an output format of the 3D video data, and ascaling factor.
 3. The method of claim 2, wherein the input format ofthe 3D video data is a left-and-right input format and the output formatof the 3D video data is a left-and-right output format.
 4. The method ofclaim 2, wherein the input format of the 3D video data is aleft-and-right input format and the output format of the 3D video datais an over-and-under output format.
 5. The method of claim 2, whereinthe input format of the 3D video data is an over-and-under input formatand the output format of the 3D video data is a left-and-right outputformat.
 6. The method of claim 2, wherein the input format of the 3Dvideo data is an over-and-under input format and the output format ofthe 3D video data is an over-and-under output format.
 7. The method ofclaim 1, wherein the selective interconnection of the one or more of theplurality of devices in the integrated circuit is determined based on aninput pixel rate of the 3D video data and on an output pixel rate of the3D video data.
 8. The method of claim 1, wherein the selectiveinterconnection of the one or more of the plurality of devices in theintegrated circuit is determined on a picture-by-picture basis.
 9. Themethod of claim 1, comprising scaling the 3D video data in theselectively interconnected one or more of the plurality of devices inthe integrated circuit, the scaling comprising a horizontal scaling anda vertical scaling.
 10. The method of claim 1, comprising performing oneor more operations in the selectively interconnected one or more of theplurality of devices in the integrated circuit, the one or moreoperations being performed before the 3D video data is scaled, after the3D video data is scaled, or both.
 11. A system, comprising: anintegrated circuit operable to selectively route and process 3D videodata, the integrated circuit comprising a plurality of devices that areoperable to be selectively interconnected to enable the routing and theprocessing; the integrated circuit being operable to determine whetherto scale the 3D video data before the 3D video data is captured tomemory or after the captured 3D video data is retrieved from the memory;and the integrated circuit being operable to selectively interconnectone or more of the plurality of devices based on the determination. 12.The system of claim 11, wherein the integrated circuit is operable todetermine the selective interconnection of the one or more of theplurality of devices based on an input format of the 3D video data, anoutput format of the 3D video data, and a scaling factor.
 13. The systemof claim 12, wherein the input format of the 3D video data is aleft-and-right input format and the output format of the 3D video datais a left-and-right output format.
 14. The system of claim 12, whereinthe input format of the 3D video data is a left-and-right input formatand the output format of the 3D video data is an over-and-under outputformat.
 15. The system of claim 12, wherein the input format of the 3Dvideo data is an over-and-under input format and the output format ofthe 3D video data is a left-and-right output format.
 16. The system ofclaim 12, wherein the input format of the 3D video data is anover-and-under input format and the output format of the 3D video datais an over-and-under output format.
 17. The system of claim 11, whereinthe integrated circuit is operable to determine the selectiveinterconnection of the one or more of the plurality of devices based onan input pixel rate of the 3D video data and on an output pixel rate ofthe 3D video data.
 18. The system of claim 11, wherein the integratedcircuit is operable to determine the selective interconnection of theone or more of the plurality of devices on a picture-by-picture basis.19. The system of claim 11, wherein the selectively interconnected oneor more of the plurality of devices are operable to horizontally scalethe 3D video data and to vertically scale the 3D video data.
 20. Thesystem of claim 19, wherein the selectively interconnected one or moreof the plurality of devices are operable to perform one or moreoperations on the 3D video data before the 3D video data is scaled,after the 3D video data is scaled, or both.